Comments on: Elijah Miller’s NEC v30 on a Pi hat

By: p2mate

p2mate — Sat, 05 Jun 2021 10:08:57 +0000

Obviously reducing the timer tick frequency will make the computer look faster for SI because SI uses this timer as its clock. Given that the timer period on an XT was 1.19318MHz / 65536, I think usleep(33927) should be a more accurate emulation. However this doesn’t account for extra delays introduced by thread scheduling etc.

By: neozeed

neozeed — Fri, 04 Jun 2021 05:47:04 +0000

In reply to raijinkai. I remember something about some universal hotplug system, in some way this is what PReP/CHrP was a generic PC with a different processor but where it fell flat was it being tied to POWER instead of allowing different processors, let alone something like the PowerPC 615.

By: raijinkai

raijinkai — Fri, 04 Jun 2021 03:53:18 +0000

AMD Hypertransport bus had provisions to connect different architecture CPUs to the same bus, with full interaction between them in master/slave configuration (Boot CPU and its “coprocessor”). It was said to give PCs the same powers than Amiga had years back with its Zorro bus compatible with “personality” CPU cards. Unfortunately this never got any mainstream board implementation, besides some rare Xilinx networking accelerators sold in 200x. Would have been nice to team it with virtualization extensions to have “Accelerated” VM sessions of any architecture, as long as there would be a “personality card” available for it. Imagine having in the same x86_64-PC “accelerated” VM sessions booting ARM, RiscV, SPARC, PPC (was the main objective back then, in order to emulate macOS PPC)…